Cos/mos phase comparator for monolithic integration

ABSTRACT

A phase comparator integrated circuit apparatus for comparing a pair of AC signals and providing a substantially pure DC output. The phase converter utilizes the time difference between pulses from two different input signals to provide a DC voltage which is free from AC ripple.

United States Patent Donoghue 1 June 27, 1972 COS/MOS PHASE COMPARATORFOR [56] References Cited MONOLITHIC INTEGRATION UNITED STATES PATENTSInventor: William J- Donoghue. Somerset. 3,495,096 2/l970 Blachowicz etal. .328/133 x 73 Assisnee; The United States America as 3,521,0847/1970 JOIICS i 307/232 represented b h s m e 1,- 3,575,665 4/1971 Honma..307/232 X Force Primary Examiner-Donald D. Forrer '[22] Flled' 1971Assistant Examiner-R. C. Woodbridge [2]] App]. No.: 173,896Attorney-Harry A. Herbert, Jr. et al.

52 us. Cl .307/232, 307/228, 307/246, [571 ABSTRACT 307/297- 307/304328/133 328/51 A phase comparator integrated circuit apparatus forcompar- [51 lllt. Cl. .1103! 13/00 ing a pair of AC signals andproviding a Substantially pure DC [58] Field of Search ..307/228, 232,246, 251, 297, output. The phase Convener umizes the time diffemnce pmsRAMP GEN.

REGULATOR between pulses from two difierent input signals to provide aDC voltage which is free from AC ripple.

3 Claims, 3 Drawing Figures FEED BncK smass F 53 75? 5741a? 5111555 ICOS/ MOS PHASE COMPARATOR FOR MONOLITHIC INTEGRATION BACKGROUND OF THEINVENTION The present invention relates broadly to a phase comparatorapparatus and in particular to a MOS integrated circuit phase comparatorproviding a substantially pure DC output signal from a pair of input ACsignals.

Conventional prior art phase detectors to provide phase comparisonsbetween alternating current signals exist in many forms. Since thecomparison that is required is between alternating current signals and,in general, the primary interest exists in a pure DC voltage which isproportional to the phase difi'erence between the two input signals, themagnitude of the AC ripple in the output of the phase detector wlu'ch iscaused by the input signals, creates a problem that is not easilyeliminated. To reduce frequency modulation of the output signal presentfrequency synthesizer subsystems require filtering on the output of thestandard phase comparators use in their phase-locked loop. Thisfiltering is harmful to the operation of the frequency synthesizer inthat it reduces the frequency response of the loop. One object of thisinvention is to reduce the output noise of the phase comparator so as toeliminate as much filtering as possible and still maintain an acceptableamount of incidental frequency modulation. The present invention isintended for use in a phase-locked loop of a frequency synthesizer whichcontrols a voltage controlled oscillator.

Among the primary requirements for operation in such a critical loop arethat the phase comparator be capable of producing a very pure DC voltageoutput and a wide swing in the output voltage. The primary reason forthese particular requirements is to enable the circuit to provide astable fixed frequency output from the voltage controlled oscillator fora fixed DC input voltage. Any AC ripple that may be present in the DCinput voltage from the phase comparator would result in an undesiredfrequency modulation condition. Additionally, a wide output voltageswing from the phase comparator is necessary to bring the phase-lockedloop into lock. The approach which would provide the purest DC voltageoutput was a sampling and hold technique. Usually in other techniques ofphase comparison some amplification is required to produce enough outputvoltage swing. Thus, in amplifying the output'signal, the AC ripple isalso amplified. The present invention avoids the common pitfalls whichare encountered in the prior art devices. Further, an all MOS approachhas been utilized since it is a low gain application, and the COS/MOSsampling gates are ideal for the sampling and hold process.

SUMMARY OF THE INVENTION The present invention utilizes a sample andhold technique to provide a phase comparator integrated circuitapparatus with a DC voltage output that is free from AC ripple. Oneinput alternating current signal R) is used to generate a ramp waveformwhile the other signal N) is used to sample this ramp, and the sampledvoltage relative to their phase difference is maintained on storagedevices. The time difierence between the pulses from the two differenceinput signals is ap plied to an amplifier stage to provide a DC voltageoutput which is proportional to the time difference.

It is one object of the invention, therefore, to provide an improvedintegrated circuit phase comparator apparatus utilizing sample and holdcircuitry to determine the phase difference between a pair ofalternating current input signals.

It is another object of the invention to provide an improved integratedcircuit phase comparator apparatus having a substantially pure DCvoltage output which is free from AC ripple.

It is yet another object of the invention to provide an improvedintegrated circuit phase comparator apparatus having a wide outputvoltage swing to bring the phase-locked loop into lock.

These and other advantages, objects and features of the invention willbecome more apparent from the following detailed description when takenin conjunction with the illustrative embodiment in the accompanyingdrawings.

DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram of the integratedcircuit phase comparator apparatus in accordance with this invention;

FIG. 1a is a schematic diagram of a p-channel MOSFET transistor; and,

FIG. 2 is a graphical representation of the waveforms which are utilizedwithin the phase comparator apparatus.

DESCRIPTION OF PREFERRED EMBODIMENT Referring now to FIG. 1, there isshown a phase comparator apparatus having a ramp generator 10 which iscomprised of a unity gain amplifier l1 and a triggering means 12 toprovide a voltage ramp output signal 13. A sample and hold circuit 14 isconnected to the ramp generator 10 to receive the voltage ramp outputsignal 13 which was generated by a first alternating current signal, R.A second alternating current signal, N, is applied to an invertercircuit 15 to obtain the complementary signal, N. Both signals, N and N,are utilized in the sample and hold circuit 14 to sample the voltageramp output signal 13. The feedback stages 16 receive and amplify theramp' signal 13 which is then applied to the sample and hold circuit 14at source follower stages, S.F.1, S.F.2. The DC output voltage of thesample and hold circuit 14 is applied to the output amplifier unit 17 tobe amplified prior to use in the frequency synthesizer (not shown). Thepure DC output voltage appears at terminal 20. A bias output regulatorprovides control signals to the output amplifier unit 17, the bias rampgenerator regulator unit 19 and the ramp generator unit 10. The biasramp generator regulator unit 19 provides an additional control signalto the ramp generator unit 10.

The present invention may be used in a phase-locked loop of a frequencysynthesizer where it controls a voltage controlled oscillator. Theprimary requirements are that the phase comparator produce a very pureDC output and have a wide swing in output voltage. The reason for theserequirements are that the circuit should produce a fixed frequencyoutput from the voltage controlled oscillator for a fixed DC voltage,and any AC ripple from the phase comparator would result in frequencymodulation. A wide output voltage swing is required to bring the phaselocked loop into lock. The complete phase comparator circuit may beimplemented by using 39 P-channel devices and four N-channel devices asis shown in simplified form in FIG. 1. FIG. 1a illustrates a P- channelMOSFET transistor having a gate 50, a drain 51, a substrate contact 53and a source 52. In the phase comparator circuit the source of atransistor is usually most positive. The circuit operates as follows.The first signal, R is applied to the ramp generator 10 and triggers aramp 13 (shown in detail in FIG. 2). The ramp voltage is then sampledthrough a COS/MOS sampling gate by the second signal, N, and thissampled voltage is held on capacitor C The signal appearing on C issampled after the first sampling gate opens out of phase) and theresulting voltage is held on capacitor C,. This double sampling helps toeliminate some of the N and ramp signal feedthrough in the waveforms atcapacitors C C which are shown in FIG. 2. The greater the timedifference between the R and N signals, the higher the DC output voltageof the circuit. The capacitors, C and C are external components to theintegrated circuit phase comparator.

The ramp generator 10 is a bootstrap sweep circuit. Capacitor C isdischarged to ground by the R signal through an N- channel device, 22,then it is allowed to charge back toward +12V through an externalresistor, R A constant current is used to charge capacitor C since aconstant voltage is maintained across resistor R by positive feedbackthrough unity gain MOS amplifier 11. The output voltage of the amplifieris independent of any mobility variations, therefore, the ramp generatoroutput should not vary with mobility. The unity gain amplifier 11 outputdepends only on the width to length ratios of devices. The COS/MOSsampling gates help to eliminate any pulse feedthrough by making thegate-to-source capacitance of the N- and P-channel units equal. Thecapacitor C is much larger than capacitor C in this application, sincecapacitor C, must charge quickly and capacitor C has the remainder ofthe cycle to charge. There is some ramp voltage feedthrough whichappears on capacitor C (through the open COS/MOS gates). The feedbackstages 16 help to eliminate this feedthrough (which would cause ACripple) by degeneratively feeding back some of the ramp voltagewaveform. The feedback stages 16 also provide a DC bias for the twosource follower stages (S.F.l and S.F.2). The output stages 17 providesome amplification to produce the output voltage swing which is requiredin the frequency synthesizer application.

The two biasing regulator networks 18,19 provide V threshold voltageregulation (and AV, correction) for the ramp generator 10 and the outputamplifier stages 17. The AV threshold regulation can be varied bychanging the widthto-length ratios between devices in the level shiftingsections of each regulator. Computer design was used for the AVcorrection. A zener diode and some filtering (not shown) may be used onthe +12 volt supply to maintain the DC level of the output independentof supply voltage and present any noise feedthrough from the supply. Thecircuit exhibits a 7 volt output swing (for a +12V supply) for 360 phasechange between R and N, and will operate over a frequency change of 600Hz and 50 Kc.

While in accordance with the provisions of the statutes, I haveillustrated and described the best forms of the invention now known tome, it will be apparent to those skilled in the art that changes may bemade in the form of the apparatus disclosed without departing from thespirit of the invention as set forth in the appended claims, and that insome cases certain features of the invention may be used to advantagewithout a corresponding use of other features.

I claim:

1. An integrated circuit phase comparator apparatus for comparing a pairof AC signals and producing a DC output voltage comprising incombination:

a ramp generator to provide a ramp output voltage, said ramp generatorreceiving a first AC signal, said ramp generator generating said rampoutput voltage in response to said first AC signal,

a sample and hold circuit to receive said ramp output voltage, saidsample and hold circuit utilizing a second AC signal to sample said rampoutput voltage, said sampled output voltage being stored in a firstcapacitor, said sampled output voltage being sampled by the complementof said second AC signal, said doubly sampled output voltage beingstored in a second capacitor,

a feedback circuit to receive said ramp output voltage from said sampleand hold circuit, said feedback circuit degeneratively feeding back aportion of said ramp output voltage to said sample and hold circuit,

an output amplifier unit receiving said output voltage from said secondcapacitor, said output amplifier unit amplifying said output voltage toprovide a DC output voltage signal, I

a bias ramp generator regulator to provide threshold voltage regulationto said ramp generator, and,

a bias output regulator to provide threshold voltage regulation to saidoutput amplifier unit, said bias ramp generator regulator and said rampgenerator.

2. An integrated circuit phase comparator apparatus as described inclaim 1 wherein said ramp generator comprises:

a unity gain amplifier to provide a constant voltage across a resistorby positive feedback through said unity gain amplifier, said constantvoltage across said resistor provide a constant current, said constantcurrent charges a third capacitor, said third capacitor is discharged toground by said first AC signal through an N-channel device to providesaid ramp output voltage.

3. An integrated circuit phase comparator apparatus as described inclaim 1 wherein said sample and hold circuit comprises:

a first source follower circuit which comprises:

a pair of P-channel devices connected in series between ground and +12volts supply,

a N-channel device connected in parallel with a P-channel device toreceive said ramp output voltage from said P- channel device pair, saidN-channel device receiving said second AC signal and said P-channeldevice receiving said second AC signal complement to charge said firstcapacitor, and

a second source follower circuit which comprises:

a pair of P-channel devices connected in series between ground and +12volts supply,

a N-channel device connected in parallel with a P-channel device toreceive said sampled output voltage from said first capacitor, saidN-channel device receiving said second AC signal complement and saidP-channel device receiving said second AC signal to charge said secondcapacitor.

1. An integrated circuit phase comparator apparatus for comparing a pairof AC signals and producing a DC output voltage comprising incombination: a ramp generator to provide a ramp output voltage, saidramp generator receiving a first AC signal, said ramp generatorgenerating said ramp output voltage in response to said first AC signal,a sample and hold circuit to receive said ramp output voltage, saidsample and hold circuit utilizing a second AC signal to sample said rampoutput voltage, said sampled output voltage being stored in a firstcapacitor, said sampled output voltage being sampled by the complementof said second AC signal, said doubly sampled output voltage beingstored in a second capacitor, a feedback circuit to receive said rampoutput voltage from said sample and hold circuit, said feedback circuitdegeneratively feeding back a portion of said ramp output voltage tosaid sample and hold circuit, an output amplifier unit receiving saidoutput voltage from said second capacitor, said output amplifier unitamplifying said output voltage to provide a DC output voltage signal, abias ramp generator regulator to provide threshold voltage regulation tosaid ramp generator, and, a bias output regulator to provide thresholdvoltage regulation to said output amplifier unit, said bias rampgenerator regulator and said ramp generator.
 2. An integrated circuitphase comparator apparatus as described in claim 1 wherein said rampgenerator comprises: a unity gain amplifier to provide a constantvoltage across a resistor by positive feedback through said unity gainamplifier, said constant voltage across said resistor provide a constantcurrent, said constant current charges a third capacitor, said thirdcapacitor is discharged to ground by said first AC signal through anN-channel device to provide said ramp output voltage.
 3. An integratedcircuit phase comparator apparatus as described in claim 1 wherein saidsample and hold circuit comprises: a first source follower circuit whichcomprises: a pair of P-channel devices connected in series betweenground and +12 volts supply, a N-channel device connected in parallelwith a P-channel device to receive said ramp output voltage from saidP-channel device pair, said N-channel device receiving said second ACsignal and said P-channel device receiving said second AC signalcomplement to charge said first capacitor, and a second source followercircuit which comprises: a pair of P-channel devices connected in seriesbetween ground and +12 volts supply, a N-channel device connected inparallel with a P-channel device to receive said sampled output voltagefrom said first capacitor, said N-channel device receiving said secondAC signal complement and said P-channel device receiving said second ACsignal to charge said second capacitor.